Successfully built | Mainboard - v.0.2 |
Schematics - v.0.2 (rev.3.16a) | |
Board layout - v.0.2 (rev.3.16a) |
The component layer (above) is drawn in red and the opposite layer in blue. The last two pages of this document show the outlines of the PAL coder board, floppy interface board (v.1.0 on the page before the last and v.1.1 on the last page) and modifications board, overlayed on the placement of the mainboard components. The associated Gerber files for this mainboard, can be downloaded as a ZIP archive. |
Board layout for the modifications module (NMI + 80 characters/line) rev.0.4 | |
The Gerber files for this board, as a ZIP archive. | |
Jumper settings for mainboard v.0.2 (rev.3.16a)
This mainboard contains a total of 23 configuration jumpers. Most are used for choosing one of the 4 hardware configurations described at the beginning of this page. The rest provide other functions. A full setting description for all jumpers - together with the number of the page in the v.0.2 schematics showing each of the jumpers - is given below:
Building the mainboard
Next I will make a few comments regarding the actual assembly of the mainboard, illustrated with some snapshots saved with the TV tuner in my PC. I have used the TV Tuner with CoBra successfully, 20 years ago in Europe (PAL TV Tuner) as well as presently (NTSC TV Tuner). The TV standard of the Tuner is not relevant, as long as the composite video output (b/w or color) from CoBra is connected to the tuner through the video in connector (usually RCA), and the TV standard is set to PAL (in the TV software used, eg. I used tvtime). Images below are b/w because at the time I took the snapshot I didn't have a PAL coder assembled yet.![]() |
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Problems encountered during actual assembly:
1. The problem of noise over long circuit tracks
After I finished assembling the prototype, while doing tests on it, I noticed on several occasions a symptom like the one in the screenshot below:![]() |
2. The problem of refreshing the dynamic memories
Another problem I encountered while experimenting with this mainboard version (v.0.2) came up when I tried to replace the MMN4164-3 chips in bank #3. (system memory) with TMS4164-20 memories (200 ns access time), of which I had ordered a bunch, to last me for about 10 computers. Well, after installing TMS4164-20 chips in the sockets of bank #3, I noticed a strange phenomenon: after loading Basic and taking a 15-20 second break (no key pressed), any key press would cause a Basic reset or even a total system corruption. A similar phenomenon would happen in Devil, CP/M or Opus, where after a certain point a corruption would occur. If, instead, right after loading Basic I would continuously press keys entering commands like BORDER x, PAPER y etc. without breaks bigger than 5-10 secunde, all commands would execute correctly without any error and the system would not reset anymore or get corrupted. I squeezed my brains quite a while trying to figure this out (a few weeks) with no success. I did a test replacing the video memory (where I had 120 ns NEC memories) with TMS4164-20 memories, and I noticed that these chips would work perfectly as video memory, without errors. So the memories themselves were not defective... Eventually, trying to think logically, I pondered the fact that if the MMN4164-3 memories worked correctly (even though they needed a 150 pF delay cap on RAS) and the TMS4164-20 memories did not (as system memory), then that means there must be a difference in the manufacturing processes of the two. So I started browsing the Microelectronica catalogue showing the datasheet for these memories, in parallel with the datasheet for the TMS4164 memories (manufactured by Texas Instruments). And so, in the 14th hour, I figured that the Texas Instruments memories require an 8 bit refresh address (256 refresh cycles) unlike the Microelectronica memories (and also unlike most of the 4164 memories made by other manufacturers) which are designed for 128 refresh cycles. Once I realized what the trouble was, I started thinking how I could "generate" the 8th bit for the refresh address on-the-fly, so I can still use this memory stock I had already wasted a lot of money on. And I designed the circuit below, which I basically built "in the air" using wires and attached to the mainboard also with wires. I installed it and then powered up the mainboard, and this time the problem vanished completely. Everything was working perfectly, Basic, Devil, OPUS, CP/M, and the interesting part is no delay capacitors were required anymore for RAS or CAS to the system memory. These 200 ns memories fit CoBra like a glove! My conclusion is that for CoBra, the best dynamic memories are those with 200 ns access time. That at least for the combination of TTLs I used (LS everywhere, except the 4 video address multiplexers which are Schottky (S), the circuits U23 (74AS20), U18 and U42 (74AS00) in the 80K modification and the circuit U55 (74AS00) in the configurator and selector circuit).