• Basic configuration, with a total of 64 KB RAM addressable (4 banks DRAM of 16KB each).
• The "64KB modified" configuration, where banks #0, #2 and #3 having 16KB each are replaced by a single 64 KB bank of which only 48 KB are addressed.
• The "80KB modified" configuration, which includes the "64KB modification" plus the capability to fully address the 80 KB total RAM installed (in CP/M).
• The "80 chars/line in CP/M" configuration, which includes the "80KB modification" plus it extends the displayable text area în CP/M by using parts of the border areas to the left and right. With this hardware modification and a modified CP/M operating system, using characters half as wide as the standard, 80 characters per text line in CP/M can be simultaneously displayed.

Jumper settings for mainboard v.0.2 (rev.3.16a)

Building the mainboard

• For the video memory (VRAM, bank #1) I used both 120 ns and 200 ns access time memories, In both cases the video memory worked correctly. For the DRAM memory (banks #0, #2, #3) I noticed while experimenting that only the chips with an access time of (minimum) 200 ns allow a correct operation. Also the chips must allow maintaining data at their outputs indefinitely when their CAS inputs are held at "0" (the majority of DRAM chips have this feature).
• For a correct operation, the video memory (memory bank #1) required the use of 74ALS153 for U03, U20, U22, U39. When using 74LS153 I couldn't get it to operate correctly, the image being corrupted from the startup configuration.
• Multiplexer U51 (74157) - also part of the video address multiplexer circuit, can be either 74LS157 or 74S157, operation is correct in both cases.
• The type of multiplexers U41 and U58 (74157) in the DRAM memory circuit depends on the access time of memories used in banks #0, #2 and #3. Thus, for memories with a high access time (200 ns) I had to use 74S157, and for memories with a low access time (120 ns) I had to use 74LS157. Yet the 120 ns memories DID NOT WORK CORRECTLY even with 74LS157. Using LS ICs improved their behaviour considerably but did not allow a 100% correct operation. My conclusion is that the system memory requires DRAM memories with a high access time (at least 200 ns).
• In order to minimize the (extra) propagation time through the 80K RAM modification circuit, I used 74AS00 for U18 and U42 and 74AS20 for U23. Also, in order to minimize the difference between propagation times of NCS0, NCS1, NCS2 and NCS3 I decided to use 74AS00 for U55 too. I have to say though I did not notice any difference between using AS and LS integrated circuits in these two cases, but since logically it seemed more correct, I used AS anyway.
• Regarding the delay capacitors used, the only ones who really proved necessary were these:
  • CCC with a value of 560 pF (pag.1 - Memory access prioritizer and command logic),
    
  • C49 with a value of 330 pF (pag.3 - Configurator and selector circuit, the 80K RAM modification)
    The absence of this capacitor causes behaviours (in Basic and Devil) the kind of those in the snapshots below:
    
    
    
  • A capacitor not prescribed by the schematics but whose necessity was experimentally determined, with a value of 150 pF, connected directly to pins 4 of dynamic memories (banks #0, #2 and #3) in order to add a delay to RAS (and as a side effect to CAS too) for the system memory. (pag.8 - "Dynamic memory circuit - pag.1/2"). Basically a capacitor to adjust the timing for RAS and/or CAS to memory in order to correctly access the dynamic memory (system memory). This capacitor was required when using MMN4164-3 chips for the system memory (manufactured at Microelectronica). I don't know for sure what is their access time, but the catalogue says it's between 200 and 300 ns. Afterwards I also did tests using TMS4164-20 DRAM memories for the system memory. Well, with these I did not have to use any kind of delay capacitors on RAS or CAS to the system memory. Hence I concluded that 200 ns access time memories are the ideal DRAM memories for CoBra. I will open a little bracket here in order to show the screenshot below, depicting what will be shown on the screen when access to the system memory is not properly tuned and loading Basic, Devil, Opus or anything like that is attempted using the "B" key from the startup configuration:
    
    
    
  • A 150 pF capacitor (also not prescribed by the schematics), connected to 3 of U36 (pag.3 - "Configurator and selector circuit"). This was required to delay the RFSH signal so that the falling edge of BNRFSH from the CPU would get to the clock input U36/3 (negated through U53/2) AFTER bit 7 of register R in the CPU became available and stable on the BA7 address line. To explain in more detail, I will quote what the CoBra hardware manual says: at power up, in the startup configuration, register R in the CPU has bit 7 set to 1. Then, when a key is pressed indicating the operating system chosen next, this bit is reset to 0 and appears on address line BA7 of the address bus during the first refresh cycle after the instruction who reset it. The moment is marked by the activation (transition to "0") of the RFSH signal generated by the CPU. This falling edge of BNRFSH is negated by U53/2 and transformed in rising edge for the clock input of flip-flop U36 (7474 uses rising clock edges). So the falling edge of BNRFSH should load flip-flop U36/5+6 with the data bit supplied on the address line BA7. The problem is that if we check the official documentation of Z80, we learn that (see the image below extracted from the manual, last half of the M1 cycle) the refresh addresses (BA0-BA7) are not guaranteed to be stable except during MREQ activation time. MREQ is activated half a CPU clock period after RFSH is activated, and RFSH is activated simultaneously with refresh addresses becoming available on the address bus.
    
    
    
    In other words, the falling edge of RFSH occurs too early to sample the refresh address on the address bus because this address is only guaranteed to be stable half a CPU clock period later. The truth is, the CoBra schematics have inverter U53 inserted on BNRFSH before U36, and BA7 is takedn directly to U36, so BNRFSH already has some delay from BA7, which in the case of both mainboards assembled by me back in the 90's was sufficient to ensure a correct operation. But now, when I built this prototype, for some reason this delay was not sufficient anymore, and my practical problem was that when pressing the "D" key in the startup configuration in order to load CP/M from disk, the border would only flash once briefly to blue, come back to black and then the computer would freeze, not reading any more keys and the disk drive would not spin the disk to read it. That because signal LO6, instead of staying at "1" for the CP/M configuration, would go to "0", which was visualized with the logical probe. Fortunately, on the forum I met YO3GHM who had the patience and kindness to analyze my problem and came up with the delivering solution, a delay capacitor on U36/3 (experientia docet...). As soon as I applied it, the mainboard started loading the disk operating system correctly. The interesting fact is that in DEVIL (BASIC using floppy disk for CoBra) disk operations would take place perfectly, commands CAT and LOAD had no problems. That's because LO6 had no problems switching to "0" (for the BASIC/DEVIL hardware configuration) but only had problems staying at "1" (for the CP/M hardware configuration).

Problems encountered during actual assembly:

1. The problem of noise over long circuit tracks

2. The problem of refreshing the dynamic memories

	A few comments are needed regarding these images: Compared with the schematics and the board layout presented above, I had to make a few changes / improvements at the time of the actual assembly. They are visible in these images on the right side of the mainboard, in the free space between the two TTL blocks where, in the original 1986 mainboard version, the 2KB EPROM column used to be. When assembling the mainboard, the 3-input diode AND gate in the 80KB RAM Modification did not behave correctly, so I decided at the last moment to replace it with a gate from a 7411. I put this 7411 in a socket, 6 leads of which I stuck in the mounting holes originally meant for the 3 diodes in the AND gate. The rest of the socket leads are bent sideways horizontally, being left completely above the circuit board, but in between the leads and the board I slipped some pieces of white paper, visible in these images, to make sure the leads stay fully separated electrically from the circuit board tracks. I used a second gate of this 7411 for the 8-bit DRAM refresh circuit, since in my particular case I needed this, because the DRAM chips I got were made by Texas Instruments, and this manufacturer, at that time, made them with an 8-bit refresh. I was not aware of this until I physically put them on the board and I noticed they don't work correctly (see the comment a little further above). But here, the extra 7411 IC mentioned above came in handy, I used a second gate from it for the 8-bit DRAM refresh circuit. The other two ICs in this circuit (7474 and 74S157) are mounted in sockets too, but the sockets are turned upside down, as seen in these images, in order to wire everything up easier. That's pretty much the story with the wiry mess visible in the middle of the mainboard. But these changes were only needed in my particular case. As far as I know, most of those who assembled this mainboard using the schematics above had no issues with the diode gate and neither used 8-bit refresh memories, so these changes are shown here only for reference. They are not part of the "official" rev.3.16a mainboard schematics.